General purpose registers or a “register file” are an essential component of a data processing system's processing architecture. For instance, a microprocessor or central processing unit (CPU) of a data processing system retrieves and stores data from and to one or more general purpose registers to process instructions. These registers allow the data processing system to perform instructions more efficiently. Many prior microprocessor architectures use sixteen general purpose registers designated, e.g., R0 through R15, and operate in different processor modes.
Prior microprocessor architectures that use such general purpose registers also process reduced instruction set computer (RISC) instructions and operate in six different processor modes: user (USR) mode, fast interrupt request (FIQ) mode, interrupt request (IRQ) mode, supervisor (SVC) mode, undefined instruction (UND) mode, and abort, exception (ABT) mode. The user mode is typically used for executing user applications. The other modes are “exception handling” modes and halt a user application in the user mode, e.g., responding to an interrupt request. For the exception handling modes, physical access to some of the general purpose registers is performed through multiple memory units of “banked” registers that are mapped to the same general purpose registers, to improve exception handling processing. That is, depending on the exception handling mode, separate and distinct registers are accessed. “Unbanked” general purpose registers do not map to banked registers and are accessed directly in all processor modes.
FIG. 1 illustrates “unbanked” and “banked” general purpose registers for this prior architecture. As shown, general purpose registers 100 includes sixteen registers R0 through R14 and one register that stores a program counter (PC). General purpose registers 100 are divided into unbanked registers 112 and banked registers 111. Unbanked registers 112 correspond to registers R0 through R7 and banked registers 111 correspond to registers R8 through R14. Banked registers 111 map to FIQ banked registers 102, IRQ banked registers 104, SVC banked registers 106, UND banked registers 108, and ABT banked registers 110 for their respective exception handling processor modes. For this prior architecture, general purpose registers R8 through R14 are mapped to multiple memory units, i.e., five separate and distinct banked registers, for different exception handling modes.
For instance, during the interrupt request, supervisor, undefined instruction, or abort exception handling modes, access to general purpose registers R13 through R14 is performed using IRQ, SVC, UND, and ABT banked registers 104, 106, 108, and 110, respectively, instead of registers R13 or R14 of general purpose registers 100. Similarly, during fast interrupt request exception handling mode, access to general purpose registers R8 through R14 is performed using FIQ banked registers 102, instead of registers R8 through R14 of general purpose registers 100. Using these banked registers avoids physical access to the preserved data in general purpose registers 100 corresponding to the respective exception handling modes.
In this manner, for the exception handling modes, physical access to some general purpose registers 100, i.e., R8 through R14 or R13 through R14, is performed using multiple memory units of respective banked registers to improve exception handling. A disadvantage, however, of using banked registers is that it requires a special type of naming scheme to distinguish between the different types of banked registers for the different types of exception handling modes, which increases processing overhead. Furthermore, such a general purpose register or “register file” scheme inefficiently accesses general purpose registers by requiring access to multiple memory units of banked registers for different exception handling modes. In other words, the prior register file requires memory access to five separate and distinct memory units for the five different exception handling modes.
There exists, therefore, a need for an improved scheme for general purpose registers or register files without using multiple banked registers for different processor modes.